Getting XST (Xilinx' synthesis tool) to infer RAM or ROM that is dual-port requires some tricks.
For some reason, the two ports must be described by separate processes. Furthermore, an unusual VHDL construct, a
shared variable, is needed 1.
Below is a listing of my parameterized module for dual-port RAM. It will successfully infer dual-port RAM, as desired, with XST. Remove the write enable-signals and write logic to get ROM instead of RAM. Specify width and depth with
highAddr is one less than desired depth) generics.
- The variable must be accessible through two different processes, and hence must be shared. A signal wouldn't have worked; to implement write-first behaviour in a convenient way, a variable must be used, since the data written must be accessible on the next line of code. ↩